job description
Join PERSOL as a SOC Physical Design Engineer and play a pivotal role in shaping the future of semiconductor technology. Based in the vibrant region of Badung, Bali, you will be responsible for the physical design and development of cutting-edge System-on-Chip (SoC) solutions, ensuring seamless integration and successful tapeout. This is a unique opportunity to work on innovative projects in a dynamic environment, collaborating with a team of experts to deliver high-performance semiconductor products.
As a key member of our engineering team, you will leverage your expertise in physical design methodologies, tools, and flows to optimize power, performance, and area (PPA) metrics. Your contributions will directly impact the efficiency and reliability of our SoC designs, driving technological advancements in the industry.
If you are passionate about semiconductor technology and thrive in a collaborative, fast-paced environment, we invite you to apply and be part of our mission to push the boundaries of innovation.
Responsibility
- Lead the physical design and implementation of complex SoC designs, from floor planning to tapeout.
- Collaborate with cross-functional teams, including R&D, verification, and manufacturing, to ensure design feasibility and optimization.
- Perform timing closure, power analysis, and signal integrity checks to meet PPA targets.
- Develop and maintain physical design methodologies, scripts, and flows to enhance efficiency and scalability.
- Conduct design rule checks (DRC), layout vs. schematic (LVS) verification, and other physical verification tasks.
- Optimize clock tree synthesis (CTS), placement, and routing to achieve optimal performance.
- Troubleshoot and resolve physical design issues, ensuring adherence to project timelines and quality standards.
- Document design processes, methodologies, and best practices for knowledge sharing and continuous improvement.
Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 3 years of experience in physical design for SoC or ASIC development.
- Proficiency in industry-standard EDA tools such as Cadence Innovus, Synopsys IC Compiler, or Mentor Graphics Olympus.
- Strong understanding of physical design flows, including floor planning, placement, routing, and timing closure.
- Experience with scripting languages such as Tcl, Perl, or Python for automation and tool customization.
- Knowledge of advanced semiconductor process nodes (e.g., 7nm, 5nm) and their design challenges.
- Excellent problem-solving skills and the ability to work effectively in a team-oriented environment.
- Strong communication skills and the ability to present technical information clearly and concisely.