job description
Join STATS ChipPAC, a global leader in advanced semiconductor packaging and test solutions, as a Senior R&D Engineer in Lithography. In this pivotal role, you will drive innovation by designing, qualifying, and optimizing cutting-edge lithography processes to enhance semiconductor packaging performance, reliability, and yield.
Based in the dynamic Badung region of Bali, you’ll collaborate with cross-functional teams to push the boundaries of microelectronics manufacturing. Your expertise will directly impact the development of next-generation packaging technologies, ensuring STATS ChipPAC remains at the forefront of the industry.
This is a unique opportunity to work on high-impact projects in a fast-paced, technology-driven environment while enjoying the vibrant culture and work-life balance of Bali.
Responsibility
- Lead the design, development, and optimization of advanced lithography processes for semiconductor packaging applications.
- Conduct process qualification and DOE (Design of Experiments) to improve yield, resolution, and overlay accuracy.
- Collaborate with process, equipment, and product engineering teams to integrate lithography solutions into high-volume manufacturing.
- Troubleshoot and resolve lithography-related defects, including focus, exposure, and resist performance issues.
- Develop and implement metrology and inspection methodologies to ensure process stability and control.
- Stay abreast of emerging lithography technologies (e.g., EUV, DUV, i-line) and assess their applicability to packaging workflows.
- Document and present technical findings, process improvements, and best practices to stakeholders.
- Support new product introductions (NPI) by defining lithography process windows and specifications.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or a related field.
- Minimum 5+ years of experience in semiconductor lithography, preferably in packaging or wafer fabrication.
- Hands-on experience with stepper/scanner tools (e.g., ASML, Nikon, Canon) and resist processing.
- Strong knowledge of optical lithography principles, including resolution enhancement techniques (RET) and mask optimization.
- Proficiency in data analysis tools (e.g., JMP, Python, MATLAB) and statistical process control (SPC).
- Experience with failure analysis (FA) and root-cause investigation for lithography defects.
- Excellent problem-solving, communication, and teamwork skills in a multicultural environment.
- Familiarity with semiconductor packaging processes (e.g., bumping, WLCSP, fan-out) is a plus.