job description
Join Microsoft in our mission to empower every person and every organization on the planet to achieve more. As a Senior Physical Design Engineer, you will play a pivotal role in developing cutting-edge semiconductor solutions that power the next generation of cloud, AI, and edge computing technologies.
Based in the vibrant and innovative hubs of Bali, Indonesia (Canggu, Ubud, Denpasar, or surrounding areas), youâll collaborate with a global team of experts to design, optimize, and implement high-performance, low-power integrated circuits. This is a unique opportunity to work on industry-leading projects while enjoying the work-life balance that Baliâs dynamic environment offers.
Microsoft is committed to fostering a diverse and inclusive workplace where creativity and technical excellence thrive. If youâre passionate about pushing the boundaries of physical design and want to contribute to technologies that shape the future, weâd love to hear from you.
Responsibility
- Lead the physical design of complex ASICs, SoCs, or FPGAs from RTL to GDSII, ensuring optimal performance, power, and area (PPA) metrics.
- Develop and implement floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure strategies for advanced process nodes (7nm, 5nm, or below).
- Collaborate with cross-functional teams (architecture, RTL design, verification, and manufacturing) to define and meet design specifications.
- Optimize designs for power efficiency, signal integrity, and manufacturability using industry-standard EDA tools (e.g., Cadence, Synopsys).
- Drive DFM (Design for Manufacturing) and DFT (Design for Test) methodologies to enhance yield and reliability.
- Mentor junior engineers and provide technical leadership in physical design methodologies and best practices.
- Stay abreast of emerging trends in semiconductor technology, EDA tools, and AI-driven design automation.
- Document design processes, methodologies, and results for internal knowledge sharing and compliance.
Qualifications
- Bachelorâs or Masterâs degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
- 7+ years of experience in physical design (ASIC/SoC/FPGA) with a proven track record of tape-outs in advanced nodes.
- Expertise in EDA tools such as Cadence Innovus, Synopsys ICC/ICC2, or Siemens EDA (Mentor Graphics).
- Deep understanding of timing closure, power analysis, and signal integrity (IR drop, EM, crosstalk).
- Experience with scripting languages (Tcl, Python, Perl) for automation and tool customization.
- Strong knowledge of CMOS processes, FinFET technologies, and low-power design techniques.
- Excellent problem-solving skills and the ability to debug complex physical design issues.
- Strong communication and teamwork skills, with the ability to work effectively in a global, remote team environment.