job description
Join Bitmain Development in shaping the future of AI hardware! As a Senior Physical Design Engineer, you’ll play a pivotal role in designing next-generation chips that power cutting-edge artificial intelligence and machine learning applications. Based in the vibrant tech hub of Bali, Indonesia, you’ll collaborate with a world-class team to push the boundaries of silicon innovation, optimizing performance, power efficiency, and scalability for high-performance computing.
This is a unique opportunity to work on groundbreaking projects that redefine the semiconductor industry. If you’re passionate about VLSI, floorplanning, timing closure, and low-power design, we want you on our team. Your expertise will directly impact the development of chips that drive AI advancements globally.
Bitmain offers a dynamic work environment, competitive compensation, and the chance to work alongside industry leaders in a tropical paradise. Relocation assistance may be available for exceptional candidates.
Responsibility
- Lead the physical design of high-performance AI/ML chips from RTL to GDSII, ensuring optimal PPA (Power, Performance, Area).
- Develop and implement floorplanning, placement, and routing strategies to meet stringent timing, power, and area constraints.
- Collaborate with RTL designers, verification teams, and foundries to resolve design bottlenecks and improve yield.
- Optimize clock networks, power grids, and signal integrity for advanced process nodes (e.g., 7nm, 5nm, or below).
- Perform timing closure, IR drop, and EM analysis using industry-standard EDA tools (e.g., Cadence, Synopsys).
- Drive DFM (Design for Manufacturing) improvements to enhance chip reliability and manufacturability.
- Mentor junior engineers and contribute to methodology development for physical design flows.
- Stay abreast of emerging semiconductor technologies and integrate innovations into design processes.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of experience in physical design for ASICs/SoCs.
- Proven expertise in floorplanning, placement, CTS, routing, and timing closure using tools like Cadence Innovus, Synopsys ICC2, or Fusion Compiler.
- Strong understanding of CMOS logic, static timing analysis (STA), and low-power design techniques.
- Experience with advanced process nodes (16nm/12nm/7nm/5nm) and FinFET technologies.
- Familiarity with scripting languages (Tcl, Python, Perl) for automation and flow customization.
- Knowledge of high-speed interface protocols (e.g., PCIe, HBM, DDR) is a plus.
- Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment.
- Strong communication skills in English (written and verbal).