job description
Join Anradus as a Senior IC Layout Engineer and play a pivotal role in shaping the future of semiconductor technology. Based in the vibrant and innovative hub of Canggu, Bali, you will lead the development of cutting-edge Integrated Circuit (IC) layouts from schematics to final tape-out, ensuring optimal performance, reliability, and manufacturability.
This is a unique opportunity to work on high-impact projects in a dynamic, forward-thinking environment. You will collaborate with cross-functional teams to deliver state-of-the-art microelectronic solutions that push the boundaries of technology. Whether you're optimizing floor plans, refining routing strategies, or conducting rigorous physical verification, your expertise will directly contribute to the success of next-generation IC designs.
At Anradus, we foster a culture of innovation, precision, and continuous learning. If you are passionate about IC layout design, thrive in a fast-paced setting, and want to be part of a team that drives technological advancement, we invite you to apply.
Responsibility
- Develop and optimize IC layouts from schematics, ensuring adherence to design rules and performance specifications.
- Perform floor planning, placement, and routing to meet timing, power, and area constraints.
- Conduct physical verification (DRC, LVS, ERC) to ensure layout integrity and compliance with foundry requirements.
- Collaborate with circuit designers, verification engineers, and fabrication teams to resolve layout-related issues.
- Implement post-layout optimization techniques, including parasitic extraction and EM/IR analysis, to enhance performance.
- Review and validate layouts through design reviews and sign-off checks to ensure first-pass success.
- Stay updated with the latest IC design tools, methodologies, and industry trends to drive continuous improvement.
- Mentor junior engineers and provide technical guidance to foster team growth and knowledge sharing.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
- Minimum 5+ years of experience in IC layout design, preferably in analog, mixed-signal, or RF domains.
- Proficiency in industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys Custom Designer.
- Strong understanding of CMOS process technologies, design rules, and layout-dependent effects (LDE).
- Experience with physical verification tools (e.g., Calibre, Assura) and scripting languages (e.g., Python, SKILL).
- Familiarity with post-layout simulation and parasitic extraction tools (e.g., Spectre, HSPICE).
- Excellent problem-solving skills and attention to detail in high-precision design environments.
- Strong communication and teamwork abilities to collaborate effectively in a global, cross-functional setting.