job description
Join a cutting-edge team at the forefront of next-generation AI and high-performance semiconductor innovation. As a Custom Layout Engineer specializing in Analog/Mixed-Signal (AMS) and SERDES, you will play a pivotal role in designing and optimizing advanced IC layouts that power the future of computing, communications, and AI acceleration.
Based in the vibrant tech hub of Badung, Bali, this role offers the unique opportunity to work on groundbreaking projects while enjoying the island’s dynamic work-life balance. Your expertise will directly contribute to the development of high-speed, low-power, and highly reliable mixed-signal circuits that define industry standards.
We are seeking a detail-oriented engineer with a passion for precision layout design, deep technical knowledge of AMS and SERDES architectures, and a commitment to pushing the boundaries of semiconductor performance. If you thrive in a collaborative, fast-paced environment and want to shape the future of chip design, this is your chance to make an impact.
Responsibility
- Design and implement custom IC layouts for Analog/Mixed-Signal (AMS) and SERDES circuits, ensuring optimal performance, power efficiency, and area utilization.
- Collaborate with circuit designers and verification teams to translate schematics into high-quality, manufacturable layouts.
- Perform layout vs. schematic (LVS) and design rule check (DRC) validations to ensure compliance with foundry requirements.
- Optimize layouts for high-speed signal integrity, noise immunity, and electromagnetic compatibility (EMC).
- Develop and maintain layout design guidelines and best practices for AMS and SERDES blocks.
- Work closely with fabrication teams to address manufacturing constraints and improve yield.
- Utilize advanced EDA tools (e.g., Cadence Virtuoso, Mentor Graphics) for layout design and verification.
- Stay updated with emerging semiconductor technologies and integrate innovations into layout methodologies.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field with a focus on semiconductor design.
- Minimum 5+ years of experience in custom IC layout design, with a strong portfolio in AMS and/or SERDES.
- Proficiency in Cadence Virtuoso, Mentor Graphics Pyxis, or similar EDA tools for layout and verification.
- Deep understanding of CMOS, BiCMOS, or FinFET process technologies and their layout implications.
- Experience with high-speed serial interfaces (SERDES), PLLs, ADCs/DACs, and RF circuits is highly desirable.
- Strong knowledge of design rules, parasitic extraction, and post-layout simulations.
- Excellent problem-solving skills and attention to detail in critical layout constraints.
- Ability to work in a cross-functional team and communicate technical concepts effectively.