job description
Join MSPHitect Sdn Bhd as a Senior Analog Layout Design Engineer and play a pivotal role in developing cutting-edge semiconductor solutions. Based in the vibrant tech hub of Badung, Bali, this contract position offers a unique opportunity to work on high-impact projects in the analog IC design space, contributing to innovations that power next-generation electronics.
As part of our dynamic engineering team, you will collaborate with cross-functional groups to translate complex circuit designs into efficient, high-performance layouts. Your expertise will directly influence the reliability, performance, and manufacturability of our analog and mixed-signal ICs. This role is ideal for a detail-oriented professional with a passion for precision and a drive to solve challenging technical problems in a fast-paced environment.
We offer a competitive salary range of IDR 330M – 462M per month, commensurate with experience, along with the chance to work in one of Southeast Asia’s most inspiring locations—where work-life balance meets technological excellence.
Responsibility
- Design and implement analog and mixed-signal IC layouts using industry-standard EDA tools (e.g., Cadence Virtuoso, Mentor Graphics).
- Collaborate with circuit designers to ensure layout feasibility, matching, and parasitic-aware optimization.
- Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification to ensure compliance with foundry rules.
- Optimize layouts for performance, area, and power efficiency while adhering to design specifications.
- Work closely with fabrication teams to address manufacturability and yield enhancement concerns.
- Document layout design processes, methodologies, and best practices for team reference.
- Troubleshoot and resolve layout-related issues during tape-out and post-silicon validation.
- Stay updated with emerging layout techniques, tools, and semiconductor process technologies.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
- Minimum 5+ years of experience in analog/mixed-signal IC layout design.
- Proficiency in Cadence Virtuoso, Mentor Graphics, or similar EDA tools.
- Strong understanding of CMOS, BiCMOS, or other semiconductor processes and design rules.
- Experience with DRC, LVS, and parasitic extraction tools (e.g., Calibre, Assura).
- Familiarity with EM (electromigration) and IR (voltage drop) analysis.
- Excellent problem-solving skills and attention to detail in high-precision environments.
- Strong communication and teamwork abilities to collaborate with global engineering teams.