job description
Join Realtek, a global leader in semiconductor innovation, as a Senior SOC Architect in the vibrant tech hub of Bali, Indonesia. This is a rare opportunity to shape the future of system-on-chip (SOC) designs while enjoying the islandâs dynamic work-life balance.
In this high-impact role, you will lead the validation and optimization of cutting-edge SOC architectures across emulation and post-silicon platforms, ensuring flawless performance, compliance with industry standards, and alignment with next-gen specifications. Your expertise will drive the development of high-performance, low-power solutions for consumer electronics, IoT, and AI-driven applications.
Realtek offers a collaborative, innovation-driven environment with access to state-of-the-art tools and a global network of engineering talent. Whether youâre refining microarchitectures, debugging complex silicon issues, or mentoring junior engineers, your work will directly influence the technology powering millions of devices worldwide.
Why Bali? Beyond the technical challenge, this role lets you work from one of Asiaâs most inspiring locationsâwhere tropical landscapes meet a thriving digital nomad community. Ideal for professionals seeking impact, growth, and lifestyle in equal measure.
Responsibility
- Architect and validate SOC designs from concept to production, ensuring adherence to performance, power, and area (PPA) targets.
- Lead pre-silicon emulation and post-silicon validation to identify and resolve design flaws, timing issues, and functional bugs.
- Collaborate with cross-functional teams (RTL, verification, DFT, and software) to define SOC specifications and microarchitecture.
- Develop and implement test plans, validation methodologies, and automation scripts for SOC bring-up and debugging.
- Optimize SOC designs for low-power consumption, high-speed interfaces (e.g., PCIe, USB, DDR), and security features.
- Analyze silicon data to correlate emulation results and drive root-cause analysis for failures.
- Mentor junior engineers and provide technical leadership in SOC architecture best practices.
- Stay ahead of industry trends in semiconductor technology (e.g., advanced nodes, AI accelerators, RISC-V) and integrate innovations into designs.
Qualifications
- Bachelorâs or Masterâs degree in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of experience in SOC architecture, ASIC design, or chip validation, with a focus on emulation (e.g., Synopsys ZeBu, Cadence Palladium) and post-silicon debugging.
- Deep expertise in SOC subsystems (CPU, GPU, memory controllers, interconnects, peripherals) and industry standards (AMBA, AXI, OCP).
- Hands-on experience with hardware description languages (Verilog, VHDL, SystemVerilog) and EDA tools (Cadence, Synopsys, Mentor Graphics).
- Proficient in C/C++ for embedded firmware and scripting (Python, Perl) for automation.
- Strong problem-solving skills with a track record of debugging complex silicon issues using logic analyzers, oscilloscopes, and JTAG.
- Familiarity with low-power design techniques (clock gating, power gating, DVFS) and security hardening (trust zones, cryptography).
- Excellent communication skills to articulate technical concepts to stakeholders and collaborate in a global team.