job description
Join Adecco in Bali’s thriving tech hub as a Senior/Principal Test Device Engineer (MTS) and lead cutting-edge semiconductor testing initiatives. This role offers a unique opportunity to work on advanced device characterization, test development, and yield enhancement for next-generation microelectronics. Based in the dynamic Badung region (covering Canggu, Ubud, Denpasar, and beyond), you’ll collaborate with global teams to drive innovation in a fast-paced, high-impact environment.
As a key technical contributor, you’ll design and optimize test solutions, analyze silicon performance, and ensure product reliability from prototyping to mass production. With a competitive compensation package (IDR 120M–180M/month + AWS + Variable Bonus), this role is perfect for seasoned engineers passionate about pushing the boundaries of semiconductor technology.
Adecco is a Fortune Global 500 leader in workforce solutions, connecting top talent with industry-leading clients worldwide.
Responsibility
- Develop and validate test methodologies for semiconductor devices, including analog, mixed-signal, and digital ICs.
- Lead silicon characterization and failure analysis to identify root causes and improve yield.
- Design and optimize ATE (Automatic Test Equipment) programs for high-volume manufacturing.
- Collaborate with cross-functional teams (Design, Process, Quality) to enhance device performance and reliability.
- Drive test time reduction and cost optimization without compromising quality.
- Mentor junior engineers and provide technical leadership in test strategy development.
- Stay abreast of industry trends in semiconductor testing and propose innovative solutions.
- Document test specifications, reports, and procedures in compliance with ISO/TS standards.
Qualifications
- Bachelor’s/Master’s/PhD in Electrical Engineering, Microelectronics, or related fields.
- Minimum 8+ years of experience in semiconductor test development (Senior/Principal level).
- Expertise in ATE platforms (e.g., Teradyne, Advantest, LTX-Credence) and test program debugging.
- Strong knowledge of device physics, CMOS processes, and statistical analysis (JMP, Python, or R).
- Experience with yield enhancement and DFM (Design for Manufacturability) techniques.
- Familiarity with LabVIEW, C/C++, or Verilog for test automation.
- Excellent problem-solving skills and ability to work in a fast-paced environment.
- Prior experience in a fab or OSAT (Outsourced Semiconductor Assembly and Test) is a plus.