job description
Join Xinpal as a Senior Design Verification Engineer and contribute to groundbreaking ASIC/SoC projects that shape the future of semiconductor technology. Based in the vibrant and innovative hub of Badung, Bali, youâll work alongside a dynamic team of engineers to deliver high-performance, cutting-edge solutions for global markets.
This role offers a competitive compensation package, including a 13th Month Bonus and Company Performance Bonus, ensuring your hard work is recognized and rewarded. Whether you're verifying complex designs, optimizing verification methodologies, or collaborating with cross-functional teams, youâll play a pivotal role in ensuring the reliability and efficiency of next-generation chips.
At Xinpal, we foster a culture of innovation, continuous learning, and professional growth. If youâre passionate about hardware verification, UVM, SystemVerilog, and FPGA prototyping, this is your opportunity to make a lasting impact in a fast-paced, forward-thinking environment.
Responsibility
- Develop and execute comprehensive verification plans for ASIC/SoC designs, ensuring full coverage of functional and performance requirements.
- Design and implement testbenches using SystemVerilog and UVM (Universal Verification Methodology).
- Collaborate with design engineers to identify and debug complex issues, providing actionable feedback for improvements.
- Automate verification processes to enhance efficiency, reduce manual effort, and accelerate time-to-market.
- Perform coverage analysis and closure to ensure all design specifications are thoroughly validated.
- Work with FPGA prototyping platforms to validate designs in real-world scenarios.
- Document verification methodologies, test cases, and results for compliance and future reference.
- Stay updated with industry trends and emerging technologies in semiconductor verification to drive innovation.
Qualifications
- Bachelorâs or Masterâs degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 5+ years of experience in ASIC/SoC verification, with a strong background in SystemVerilog and UVM.
- Proven expertise in testbench development, constraint-random testing, and functional coverage.
- Hands-on experience with EDA tools such as Cadence Xcelium, Synopsys VCS, or Mentor Questa.
- Familiarity with FPGA prototyping and emulation platforms is a plus.
- Strong problem-solving skills with the ability to debug complex hardware issues at the RTL and gate level.
- Excellent communication and teamwork skills to collaborate effectively with global, cross-functional teams.
- Experience with scripting languages (e.g., Python, Perl) for automation is highly desirable.