job description
Join PERSOL as a SOC Physical Design Engineer in the vibrant tech hub of Badung, Bali! This is a 1-year contract role with 2 open positions, offering a competitive salary of up to $7,000/month for the right candidate.
As a SOC Physical Design Engineer, you will play a pivotal role in the development of cutting-edge System-on-Chip (SOC) designs, ensuring optimal performance, power efficiency, and manufacturability. This position is ideal for professionals with a strong background in VLSI, RTL-to-GDSII flow, timing closure, and physical verification.
Based in Bali’s dynamic tech ecosystem, you’ll collaborate with cross-functional teams to deliver high-quality semiconductor solutions. Whether you're based in Canggu, Ubud, Denpasar, or Jimbaran, this role offers the flexibility to work in one of Southeast Asia’s most innovative and scenic locations.
If you’re passionate about chip design, floorplanning, and advanced node technologies, this is your chance to contribute to groundbreaking projects while enjoying Bali’s unique work-life balance.
Responsibility
- Develop and optimize SOC physical design from RTL to GDSII, ensuring adherence to timing, power, and area constraints.
- Perform floorplanning, placement, and routing using industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2).
- Conduct timing analysis and closure (STA) to meet performance targets.
- Collaborate with front-end and back-end teams to resolve design issues and improve chip reliability.
- Implement power network design and IR drop analysis for efficient power delivery.
- Verify physical design integrity through DRC, LVS, and ERC checks.
- Optimize clock tree synthesis (CTS) and signal integrity for high-speed designs.
- Document design methodologies and contribute to process improvements for future projects.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Minimum 3+ years of experience in SOC physical design (preferably in advanced nodes like 7nm/5nm).
- Proficiency in EDA tools (Cadence Innovus, Synopsys ICC2, Fusion Compiler, or similar).
- Strong understanding of timing closure, power analysis, and physical verification.
- Experience with Tcl/Perl scripting for automation in physical design flows.
- Familiarity with UNIX/Linux environments and version control systems (e.g., Git).
- Excellent problem-solving and debugging skills for complex SOC designs.
- Strong communication and teamwork abilities to collaborate with global teams.