job description
Join ByteDance’s Silicon Platform Team, the core R&D middleware group driving cutting-edge chip development. As a Synthesis & Static Timing Analysis (STA) Engineer, you will play a pivotal role in optimizing chip performance, power efficiency, and timing closure for next-generation semiconductor designs.
Based in the vibrant tech hubs of Bali, Indonesia (Canggu, Ubud, Denpasar, or surrounding areas), you’ll collaborate with global teams to push the boundaries of VLSI design, leveraging advanced EDA tools and methodologies. This is a unique opportunity to contribute to high-impact projects in a dynamic, innovation-driven environment.
ByteDance offers a competitive compensation package, flexible work arrangements, and the chance to work on transformative technologies that power billions of users worldwide.
Responsibility
- Develop and optimize RTL-to-GDSII synthesis flows using industry-standard tools (e.g., Synopsys Design Compiler, Cadence Genus).
- Perform comprehensive Static Timing Analysis (STA) to identify and resolve timing violations, ensuring robust chip performance.
- Collaborate with front-end and back-end design teams to define timing constraints, power budgets, and area trade-offs.
- Implement and validate low-power design techniques (e.g., clock gating, power gating) to enhance energy efficiency.
- Automate and enhance EDA toolflows using scripting (Tcl, Python) to improve productivity and design quality.
- Analyze and debug complex timing issues across different PVT corners and modes (e.g., best-case, worst-case, typical).
- Document methodologies, best practices, and design guidelines for synthesis and STA processes.
- Stay abreast of emerging EDA tools, libraries, and semiconductor technologies to drive continuous improvement.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of experience in ASIC/SoC synthesis and STA.
- Proficiency in Synopsys Design Compiler, Primetime, or Cadence Genus/Tempus for synthesis and timing analysis.
- Strong understanding of CMOS logic design, timing closure, and physical design challenges (e.g., crosstalk, IR drop).
- Experience with UPF/CPF for low-power design and verification.
- Familiarity with Tcl, Perl, or Python scripting for EDA tool automation.
- Knowledge of advanced node processes (7nm, 5nm, or below) is a plus.
- Excellent problem-solving skills and ability to debug complex timing and synthesis issues.
- Strong communication skills to collaborate with cross-functional teams in a global setting.